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nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb pc2700 and pc2100 rev 1.0 1 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. 200 pin unbuffered ddr so-dimm based on ddr333/266 512mb bit b die device features 200-pin small outline dual in-line memory module (so-dimm) unbuffered ddr so-dimm based on 110nm 512m bit die b device, organized as 64mx8 and 32mx16 ddr sdram performance: pc2700 pc2100 speed sort 6k 75b dimm cas latency 2.5 2.5 unit f ck clock frequency 166 133 mhz t ck clock cycle 6 7.5 ns f dq dq burst frequency 333 266 mhz intended for 133 and 166 mhz applications inputs and outputs are sstl-2 compatible v dd = v ddq = 2.5v 0.2v sdrams have 4 internal banks for concurrent operation differential clock inputs data is read or written on both clock edges dram dll aligns dq and dqs transitions with clock transitions. address and control signals are fully synchronous to positive clock edge programmable operation: - dimm cas latency: 2, 2.5 - burst type: sequential or interleave - burst length: 2, 4, 8 - operation: burst read and write auto refresh (cbr) and self refresh modes automatic and controlled precharge commands 7.8 s max. average periodic refresh interval serial presence detect eeprom gold contacts on module pcb available in ?green? packaging (lead & halogen free) description nt1gd64s8hb0fm, nt512d64sh8b0gm and nt256d64sh4b0gm are un-buffered 200-pin double data rate (ddr) synchronous dram small outline dual in-line memory module (so-dimm). all devices on these modules are based on nanya?s 110nm die b generation of 512m bit devices. nt1gd64s8hb0fn, nt512d64sh8b0gn and nt256d64sh4b0gn are the corresponding part numbers that are in ?green? packaging and they are identical in both physical and electrical characteristics as non-green parts. the nt1gd64s8hb0fm is organized as two ranks of 64mx64 high-speed memory array and uses sixteen 64mx8 ddr sdrams bga packages. the nt512d64sh8b0gm is organized as two ranks of 32mx64 high-speed memory array and uses eight 32mx16 ddr sdrams tsop packages. the nt256d64sh4b0gm is organized a single rank of 32mx64 high-speed memory array and uses four 32mx16 ddr sdrams tsop packages. the dimms are intended for use in applications operating up to 166 mhz clock speeds and achieves high-speed data transfer rates of up to 333 mhz. prior to any access operation, the device cas latency and burst type/ length/operation type must be programmed into the dimm by address inputs and i/o inputs ba0 and ba1 using the mode register set cycle. the so-dimm uses a serial eeprom and through the use of a standard iic protocol the serial presence-detect implementation (spd) data can be accessed. the first 128 bytes of the spd data are programmed with the module characteristics as defined by jedec.
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 2 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ordering information part number size speed power leads nt1gd64s8hb0fm-6k 128mx64 nt512d64sh8b0gm-6k 64mx64 nt256d64sh4b0gm-6k 32mx64 ddr333 devices pc2700 2.5-3-3 166mhz (6ns @ cl = 2.5) 133mhz (7.5ns @ cl = 2) nt1gd64s8hb0fm-75b 128mx64 nt512d64sh8b0gm-75b 64mx64 nt256d64sh4b0gm-75b 32mx64 ddr266 devices pc2100 2.5-3-3 133mhz (7.5ns @ cl = 2.5) 100mhz (10ns @ cl = 2) 2.5v gold ?green? part number size speed power leads nt1gd64s8hb0fn-6k 128mx64 nt512d64sh8b0gn-6k 64mx64 nt256d64sh4b0gn-6k 32mx64 ddr333 devices pc2700 2.5-3-3 166mhz (6ns @ cl = 2.5) 133mhz (7.5ns @ cl = 2) nt1gd64s8hb0fnm-75b 128mx64 NT512D64SH8B0GN-75B 64mx64 nt256d64sh4b0gn-75b 32mx64 ddr266 devices pc2100 2.5-3-3 133mhz (7.5ns @ cl = 2.5) 100mhz (10ns @ cl = 2) 2.5v gold (lead and halogen free) for the closest sales office or information, please visit: www.nanya.com nanya technology corporation hwa ya technology park 669 fu hsing 3rd rd., kueishan, taoyuan, 333, taiwan, r.o.c. tel: +886-3-328-1688
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 3 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. pin description ck0, ck1, ck2, ck0 , ck1 , ck2 differential clock inputs. dq0-dq63 data input/output cke0, cke1 clock enable dqs0-dqs7 bidirectional data strobes ras row address strobe dm0-dm7 input data mask cas column address strobe v dd power we write enable v ddq supply voltage for dqs s0 , s1 chip selects v ss ground a0-a9, a11, a12 address inputs nc no connect a10/ap address input/auto-precharge scl serial presence detect clock input ba0, ba1 sdram bank address inputs sda serial presence detect data input/output v ref ref. voltage for sstl_2 inputs sa0-2 serial presence detect address inputs v ddid v dd identification flag. v ddspd serial eeprom positive power supply pinout pin front pin back pin front pin back pin front pin back pin front pin back 1 v ref 2 v ref 51 v ss 52 v ss 101 a9 102 a8 151 dq42 152 dq46 3 v ss 4 v ss 53 dq19 54 dq23 103 v ss 104 v ss 153 dq43 154 dq47 5 dq0 6 dq4 55 dq24 56 dq28 105 a7 106 a6 155 v dd 156 v dd 7 dq1 8 dq5 57 v dd 58 v dd 107 a5 108 a4 157 v dd 158 ck1 9 v dd 10 v dd 59 dq25 60 dq29 109 a3 110 a2 159 v ss 160 ck1 11 dqs0 12 dm0 61 dqs3 62 dm3 111 a1 112 a0 161 v ss 162 v ss 13 dq2 14 dq6 63 v ss 64 v ss 113 v dd 114 v dd 163 dq48 164 dq52 15 v ss 16 v ss 65 dq26 66 dq30 115 a10/ap 116 ba1 165 dq49 166 dq53 17 dq3 18 dq7 67 dq27 68 dq31 117 ba0 118 ras 167 v dd 168 v dd 19 dq8 20 dq12 69 v dd 70 v dd 119 we 120 cas 169 dqs6 170 dm6 21 v dd 22 v dd 71 nc 72 nc 121 s0 122 s1 171 dq50 172 dq54 23 dq9 24 dq13 73 nc 74 nc 123 du 124 du 173 v ss 174 v ss 25 dqs1 26 dm1 75 v ss 76 v ss 125 v ss 126 v ss 175 dq51 176 dq55 27 v ss 28 v ss 77 dqs8 78 nc 127 dq32 128 dq36 177 dq56 178 dq60 29 dq10 30 dq14 79 nc 80 nc 129 dq33 130 dq37 179 v dd 180 v dd 31 dq11 32 dq15 81 v dd 82 v dd 131 v dd 132 v dd 181 dq57 182 dq61 33 v dd 34 v dd 83 nc 84 nc 133 dqs4 134 dm4 183 dqs7 184 dm7 35 ck0 36 v dd 85 du 86 du 135 dq34 136 dq38 185 v ss 186 v ss 37 ck0 38 v ss 87 v ss 88 v ss 137 v ss 138 v ss 187 dq58 188 dq62 39 v ss 40 v ss 89 ck2 90 v ss 139 dq35 140 dq39 189 dq59 190 dq63 41 dq16 42 dq20 91 ck2 92 v dd 141 dq40 142 dq44 191 v dd 192 v dd 43 dq17 44 dq21 93 v dd 94 v dd 143 v dd 144 v dd 193 sda 194 sa0 45 v dd 46 v dd 95 cke1 96 cke0 145 dq41 146 dq45 195 scl 196 sa1 47 dqs2 48 dm2 97 du 98 du 147 dqs5 148 dm5 197 v ddspd 198 sa2 49 dq18 50 dq22 99 a12 100 a11 149 v ss 150 v ss 199 v ddid 200 du note: all pin assignments are consistent for all 8-byte unbuffered versions.
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 4 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. input/output functional description symbol type polarity function ck0, ck1, ck2, ck0 , ck1 , ck2 (sstl) cross point the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and falling edge of ck. a delay locked loop (dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. cke0, cke1 (sstl) active high activates the ddr sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s0 , s1 (sstl) active low enables the associated ddr sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. physical bank 0 is selected by s0; bank 1 is selected by s1. ras , cas , we (sstl) active low when sampled at the positive rising edge of the clock, ras , cas , we define the operation to be executed by the sdram. v ref supply reference voltage for sstl-2 inputs v ddq supply isolated power supply for the ddr sdram output buffers to provide improved noise immunity ba0, ba1 (sstl) - selects which sdram bank is to be active. a0 - a9 a10/ap a11 - a13 (sstl) - during a bank activate command cycle, these lines define the row address when sampled at the rising clock edge. during a read or write command cycle, these lines defines the column address when sampled at the rising clock edge. in addition to the column address, ap is used to invoke auto-precharge operation at the end of the burst read or write cycle. if ap is high, auto-precharge is selected and ba0/ba1 defines the bank to be precharged. if ap is low, auto-precharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0/ba1 to control which bank(s) to precharge. if ap is high all 4 banks will be precharged regardless of the state of ba0/ba1. if ap is low, then ba0/ba1 are used to define which bank to pre-charge. dq0 - dq63 (sstl) - data and check bit input/output pins operate in the same manner as on conventional drams. dqs0 ? dqs8 (sstl) active high data strobes: output with read data, input with write data. edge aligned with read data, centered on write data. used to capture write data. dqs8 is used for ecc modules (cb0-cb7) and is not used on x64 modules. cb0 ? cb7 (sstl) - data check bit input/output pins. used on ecc modules and is not used on x64 modules. dm0 ? dm8 input active high the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dm8 is associated with check bits cb0-cb7, and is not used on x64 modules. v dd , v ss supply power and ground for the ddr sdram input buffers and core logic sa0 ? sa2 - address inputs. connected to either v dd or v ss on the system board to configure the serial presence detect eeprom address. sda - this bi-directional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v dd to act as a pull-up. scl - this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to v dd to act as a pull-up. v ddspd supply serial eeprom positive power supply.
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 5 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram 2 ranks, 16 devices, 64mx8 ddr sdrams serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 s1 dm0 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq8 dq9 dq10 dq15 dq12 dq14 dq13 dq11 dq16 dq17 dq18 dq23 dq20 dq22 dq21 dq19 dq24 dq25 dq26 dq31 dq28 dq30 dq29 dq27 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d3 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d2 dqs0 dm4 dqs4 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d0 dm1 dqs1 dqs dm2 dqs2 dm3 dqs3 dqs dq32 dq33 dq34 dq39 dq36 dq38 dq37 dq35 dq40 dq41 dq42 dq47 dq44 dq46 dq45 dq43 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d1 dqs dqs5 dm5 dq48 dq49 dq50 dq55 dq52 dq54 dq53 dq51 dq56 dq57 dq58 dq63 dq60 dq62 dq61 dq59 dqs6 dm6 dqs7 dm7 dqs s0 i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d8 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d9 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d10 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d11 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d7 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d6 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d4 dqs dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d5 dqs dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d12 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d13 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d14 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d15 dqs a0-a12 ras ba0-ba1 ba0-ba1 : sdrams d0-d15 a0-a12 : sdrams d0-d15 ras : sdrams d0-d15 cke0 we cas cas : sdrams d0-d15 cke : sdrams d0-d7 cke : sdrams d8-d15 we : sdrams d0-d15 cke1 v ddspd v ss v ref v ddid v dd /v ddq strap: see note 4 spd d0-d15 d0-d15 d0-d15 notes : 1. dq-to-i/o wring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships are maintained as shown. 3. dq/dqs/dm/dqs resistors are 22 ohms. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd is not equal to v ddq . clock wiring clock input sdrams ck0/ ck0 ck1/ ck1 ck2/ ck2 8 sdrams 8 sdrams nc * clock net wiring d0/d8 d1/d9 d2/d10 d3/d11 card edge ck0/ck1 ck0 / ck1 r=120 ohms d4/d12 d5/d13 d6/d14 d7/d15
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 6 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram 2 ranks, 8 devices, 32mx16 ddr sdrams s0 dm0 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq8 dq9 dq10 dq15 dq12 dq14 dq13 dq11 dq16 dq17 dq18 dq23 dq20 dq22 dq21 dq19 dq24 dq25 dq26 dq31 dq28 dq30 dq29 dq27 dqs0 dm4 dqs4 dm1 dqs1 dm2 dqs2 dm3 dqs3 dq32 dq33 dq34 dq39 dq36 dq38 dq37 dq35 dq40 dq41 dq42 dq47 dq44 dq46 dq45 dq43 dqs5 dm5 dq48 dq49 dq50 dq55 dq52 dq54 dq53 dq51 dq56 dq57 dq58 dq63 dq60 dq62 dq61 dq59 dqs6 dm6 dqs7 dm7 s1 serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 v ddspd v ss spd d0-d7 d0-d7 d0-d7 v dd /v ddq v ref v ddid i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 ldm cs d0 i/o 8 i/o 9 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 15 udm udqs ldqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 ldm cs d4 i/o 8 i/o 9 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 15 udm udqs ldqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 ldm cs d1 i/o 8 i/o 9 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 15 udm udqs ldqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 ldm cs d5 i/o 8 i/o 9 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 15 udm udqs ldqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 ldm cs d3 i/o 8 i/o 9 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 15 udm udqs ldqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 ldm cs d7 i/o 8 i/o 9 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 15 udm udqs ldqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 ldm cs d2 i/o 8 i/o 9 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 15 udm udqs ldqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 ldm cs d6 i/o 8 i/o 9 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 15 udm udqs ldqs notes : 1. dq wiring may differ from that described in this drawing. 2. dq/dqs/dm/cke/s relationships are maintained as shown. 3. dq/dqs/dm/dqs resistors are 22+/- 5% ohms. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd is not equal to v ddq . a0-a12 ras ba0-ba1 ba0-ba1 : sdrams d0-d7 a0-a12 : sdrams d0-d7 ras : sdrams d0-d7 cke0 we cas cas : sdrams d0-d7 cke : sdrams d0-d3 cke : sdrams d4-d7 we : sdrams d0-d7 cke1 clock wiring clock input sdrams ck0/ ck0 ck1/ ck1 ck2/ ck2 4 sdrams 4 sdrams nc * clock net wiring d0/d4 d1/d5 d2/d6 d3/d7 card edge ck0/ck1 ck0 / ck1 r=120 ohms
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 7 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram 1 rank, 4 devices, 32mx16 ddr sdrams s0 dm0 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq8 dq9 dq10 dq15 dq12 dq14 dq13 dq11 dq16 dq17 dq18 dq23 dq20 dq22 dq21 dq19 dq24 dq25 dq26 dq31 dq28 dq30 dq29 dq27 dqs0 dm4 dqs4 dm1 dqs1 dm2 dqs2 dm3 dqs3 dq32 dq33 dq34 dq39 dq36 dq38 dq37 dq35 dq40 dq41 dq42 dq47 dq44 dq46 dq45 dq43 dqs5 dm5 dq48 dq49 dq50 dq55 dq52 dq54 dq53 dq51 dq56 dq57 dq58 dq63 dq60 dq62 dq61 dq59 dqs6 dm6 dqs7 dm7 serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 v ddspd v ss spd d0-d3 d0-d3 d0-d3 v dd /v ddq v ref v ddid i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 ldm cs d0 i/o 8 i/o 9 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 15 udm udqs ldqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 ldm cs d1 i/o 8 i/o 9 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 15 udm udqs ldqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 ldm cs d3 i/o 8 i/o 9 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 15 udm udqs ldqs i/o 0 i/o 1 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 ldm cs d2 i/o 8 i/o 9 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 15 udm udqs ldqs notes : 1. dq wiring may differ from that described in this drawing. 2. dq/dqs/dm/cke/s relationships are maintained as shown. 3. dq/dqs/dm/dqs resistors are 22+/- 5% ohms. 4. v ddid strap connections (for memory device v dd , v ddq ): strap out (open): v dd = v ddq strap in (v ss ): v dd is not equal to v ddq . 2 loads ck0 ck0 ck1 ck1 ck2 ck2 2 loads 0 loads ba0-ba1 a0-a12 ras ba0-ba1 : sdrams d0-d3 a0-a12 : sdrams d0-d3 ras : sdrams d0-d3 cke0 we cas cas : sdrams d0-d3 cke : sdrams d0-d3 n.c. we : sdrams d0-d3 cke1
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 8 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. serial presence detect byte description byte description 0 number of serial pd bytes written during production 27 minimum row precharge time (t rp ) 1 total number of bytes in serial pd device 28 minimum row active to row active delay (t rrd ) 2 fundamental memory type 29 minimum ras to cas delay (t rcd ) 3 number of row addresses on assembly 30 minimum ras pulse width (t ras ) 4 number of column addresses on assembly 31 module bank density 5 number of dimm rank 32 address and command setup time before clock 6 data width of assembly 33 address and command hold time after clock 7 data width of assembly (cont?) 34 data input setup time before clock 8 voltage interface level of this assembly 35 data input hold time after clock 9 ddr sdram device cycle time cl=2.5 36-40 reserved 10 ddr sdram device access time from clock cl=2.5 41 minimum active/auto-refresh time (t rc ) 11 dimm configuration type 42 auto-refresh to active/auto-refresh command period (t rfc ) 12 refresh rate/type 43 max cycle time (t ck max ) 13 primary ddr sdram width 44 maximum dqs-dq skew time (t dqsq ) 14 error checking ddr sdram device width 45 maximum read data hold skew factor (t qhs ) 15 ddr sdram device attr: min clk delay, random col access 46 reserved 16 ddr sdram device attributes: burst length supported 47 dimm height 17 ddr sdram device attributes: number of device banks 48-61 reserved 18 ddr sdram device attributes: cas latencies supported 62 spd revision 19 ddr sdram device attributes: cs latency 63 checksum data 20 ddr sdram device attributes: we latency 64-71 manufacturer?s jedec id code 21 ddr sdram device attributes: 72 module manufacturing location 22 ddr sdram device attributes: general 73-90 module part number 23 minimum clock cycle cl=2.5 91-92 module revision code 24 maximum data access time from clock at cl=2 93-94 module manufacturing data yy= binary coded decimal year code, 0-99(decimal), 00-63(hex) ww= binary coded decimal year code, 01-52(decimal), 01-34(hex) 25 minimum clock cycle time at cl=1 95-98 module serial number 26 maximum data access time from clock at cl=1 99-127 reserved
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 9 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. spd values for nt1gd64s8hb0fm / nt1gd64s8hb0fn pc2700 (6k) pc2100 (75b) byte value hex value hex 0 128 80 128 80 1 256 08 256 08 2 sdram ddr 07 sdram ddr 07 3 13 0d 13 0d 4 11 0b 11 0b 5 2 02 2 02 6 x64 40 x64 40 7 x64 00 x64 00 8 sstl 2.5v 04 sstl 2.5v 04 9 6.0ns 60 7.5ns 75 10 7.0ns 70 7.5ns 75 11 non-parit y 00 non-parit y 00 12 sr/1x ( 7.8us ) 82 sr/1x ( 7.8us ) 82 13 x8 08 x8 08 14 n/a 00 n/a 00 15 1 clock 01 1 clock 01 16 2 , 4 , 8 0e 2 , 4 , 8 0e 17 4 04 4 04 18 2/2.5 0c 2/2.5 0c 19 0 01 0 01 20 1 02 1 02 21 differential clock 20 differential clock 20 22 0.2v tolerance c0 0.2v tolerance c0 23 7.5ns 75 10ns a0 24 0.75ns 75 0.75ns 75 25 n/a 00 n/a 00 26 n/a 00 n/a 00 27 18ns 48 20ns 50 28 12ns 30 15ns 3c 29 18ns 48 20ns 50 30 42ns 2a 45ns 2d 31 512mb 80 512mb 80 32 0.75ns 75 0.90ns 90 33 0.75ns 75 0.90ns 90 34 0.45ns 45 0.50ns 50 35 0.45ns 45 0.50ns 50 36-40 reserved 00 reserved 00 41 60ns 3c 60ns 41 42 72ns 48 75ns 4b 43 12ns 30 12ns 30 44 0.40ns 28 0.50ns 32 45 0.50ns 50 0.75ns 75 46 reserved 00 reserved 00 47 31.75mm 01 31.75mm 01 48-61 reserved 00 reserved 00 62 spd 1.0 10 spd 1.0 10 63 checksum 4e checksum 35 64-71 nanya 7f7f7f0b 00000000 nanya 7f7f7f0b 00000000 72 assembl y -- assembl y -- 73-90 module pn -- module pn -- 91-92 revision -- revision -- 93-94 year/week code -- year/week code -- 95-98 serial number -- serial number -- 99-255 reserved -- reserved --
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 10 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. spd values for nt512d64sh8b0gm / nt512d64sh8b0gn pc2700 (6k) pc2100 (75b) byte value hex value hex 0 128 80 128 80 1 256 08 256 08 2 sdram ddr 07 sdram ddr 07 3 13 0d 13 0d 4 10 0a 10 0a 5 2 02 2 02 6 x64 40 x64 40 7 x64 00 x64 00 8 sstl 2.5v 04 sstl 2.5v 04 9 6.0ns 60 7.5ns 75 10 7.0ns 70 7.5ns 75 11 non-parit y 00 non-parit y 00 12 sr/1x ( 7.8us ) 82 sr/1x ( 7.8us ) 82 13 x16 10 x16 10 14 n/a 00 n/a 00 15 1 clock 01 1 clock 01 16 2 , 4 , 8 0e 2 , 4 , 8 0e 17 4 04 4 04 18 2/2.5 0c 2/2.5 0c 19 0 01 0 01 20 1 02 1 02 21 differential clock 20 differential clock 20 22 0.2v tolerance c0 0.2v tolerance c0 23 7.5ns 75 10ns a0 24 0.75ns 75 0.75ns 75 25 n/a 00 n/a 00 26 n/a 00 n/a 00 27 18ns 48 20ns 50 28 12ns 30 15ns 3c 29 18ns 48 20ns 50 30 42ns 2a 45ns 2d 31 256mb 40 256mb 40 32 0.75ns 75 0.90ns 90 33 0.75ns 75 0.90ns 90 34 0.45ns 45 0.50ns 50 35 0.45ns 45 0.50ns 50 36-40 reserved 00 reserved 00 41 60ns 3c 65ns 41 42 72ns 48 75ns 4b 43 12ns 30 12ns 30 44 0.45ns 2d 0.50ns 32 45 0.55ns 55 0.75ns 75 46 reserved 00 reserved 00 47 31.75mm 01 31.75mm 01 48-61 reserved 00 reserved 00 62 spd 1.0 10 spd 1.0 10 63 checksum 1f checksum fc 64-71 nanya 7f7f7f0b 00000000 nanya 7f7f7f0b 00000000 72 assembl y -- assembl y -- 73-90 module pn -- module pn -- 91-92 revision -- revision -- 93-94 year/week code -- year/week code -- 95-98 serial number -- serial number -- 99-255 reserved -- reserved --
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 11 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. spd values for nt256d64sh4b0gm / nt256d64sh4b0gn pc2700 (6k) pc2100 (75b) byte value hex value hex 0 128 80 128 80 1 256 08 256 08 2 sdram ddr 07 sdram ddr 07 3 13 0d 13 0d 4 10 0a 10 0a 5 1 01 1 01 6 x64 40 x64 40 7 x64 00 x64 00 8 sstl 2.5v 04 sstl 2.5v 04 9 6.0ns 60 7.5ns 75 10 7.0ns 70 7.5ns 75 11 non-parit y 00 non-parit y 00 12 sr/1x ( 7.8us ) 82 sr/1x ( 7.8us ) 82 13 x16 10 x16 10 14 n/a 00 n/a 00 15 1 clock 01 1 clock 01 16 2 , 4 , 8 0e 2 , 4 , 8 0e 17 4 04 4 04 18 2/2.5 0c 2/2.5 0c 19 0 01 0 01 20 1 02 1 02 21 differential clock c0 differential clock c0 22 0.2v tolerance 00 0.2v tolerance 00 23 7.5ns 75 10ns a0 24 0.75ns 75 0.75ns 75 25 n/a 00 n/a 00 26 n/a 00 n/a 00 27 18ns 48 20ns 50 28 12ns 30 15ns 3c 29 18ns 48 20ns 50 30 42ns 2a 45ns 2d 31 256mb 40 256mb 40 32 0.75ns 75 0.90ns 90 33 0.75ns 75 0.90ns 90 34 0.45ns 45 0.50ns 50 35 0.45ns 45 0.50ns 50 36-40 reserved 00 reserved 00 41 60ns 3c 65ns 41 42 72ns 48 75ns 4b 43 12ns 30 12ns 30 44 0.45ns 2d 0.50ns 32 45 0.55ns 55 0.75ns 75 46 reserved 00 reserved 00 47 31.75mm 01 31.75mm 01 48-61 reserved 00 reserved 00 62 spd 1.0 10 spd 1.0 10 63 checksum 1e checksum fb 64-71 nanya 7f7f7f0b 00000000 nanya 7f7f7f0b 00000000 72 assembl y -- assembl y -- 73-90 module pn -- module pn -- 91-92 revision -- revision -- 93-94 year/week code -- year/week code -- 95-98 serial number -- serial number -- 99-255 reserved -- reserved --
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 12 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. absolute maximum ratings symbol parameter rating units v in , v out voltage on i/o pins relative to v ss -0.5 to v ddq +0.5 v v in voltage on input relative to v ss -0.5 to +3.6 v v dd voltage on v dd supply relative to v ss -0.5 to +3.6 v v ddq voltage on v ddq supply relative to v ss -0.5 to +3.6 v t a operating temperature (ambient) 0 to +70 c t stg storage temperature (plastic) -55 to +150 c p d power dissipation (per device component) 1 w i out short circuit output current 50 ma note : stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational s ections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions t a = 0 c ~ 70 c; v ddq = v dd = 2.5v 0.2v symbol parameter min max units notes v dd supply voltage 2.3 2.7 v 1 v ddq i/o supply voltage 2.3 2.7 v 1 v ss , v ssq supply voltage, i/o supply voltage 0 0 v v ref i/o reference voltage 0.49 x v ddq 0.51 x v ddq v 1, 2 v tt i/o termination voltage (system) v ref C 0.04 v ref + 0.04 v 1, 3 v ih (dc) input high (logic1) voltage v ref + 0.15 v ddq + 0.3 v 1 v il (dc) input low (logic0) voltage -0.3 v ref - 0.15 v 1 v in (dc) input voltage level, ck and ck inputs -0.3 v ddq + 0.3 v 1 v id (dc) input differential voltage, ck and ck inputs 0.30 v ddq + 0.6 v 1, 4 i i input leakage current any input 0v v in v dd ; (all other pins not under test = 0v) -10 10 a 1 i oz output leakage current (dqs are disabled; 0v v out v ddq -10 10 a 1 i oh output high current (v out = v ddq -0.373v, min v ref , min v tt ) -16.8 - ma 1 i ol output low current (v out = 0.373, max v ref , max v tt ) 16.8 - ma 1 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the dimm. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck .
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 13 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac characteristics notes 1-5 apply to the following tables; electrical characteristics and dc operating conditions, ac operating conditions, operating, standby, and refresh currents, and electrical characteristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac timing, idd, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage le vels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load. refer to the ac output load circuit below. 4. ac timing and idd tests may use a v il to v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck, ck ), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il (ac) and v ih (ac) unless otherwise specified. 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc inp ut low (high) level. ac output load circuits timing reference point v tt 50 ohms 30 pf output v out ac operating conditions t a = 0 c ~ 70 c; v ddq = v dd = 2.5v 0.2v symbol parameter/condition min max unit notes v ih (ac) input high (logic 1) voltage. v ref + 0.31 v 1, 2 v il (ac) input low (logic 0) voltage. v ref - 0.31 v 1, 2 v id (ac) input differential voltage, ck and ck inputs 0.62 v ddq + 0.6 v 1, 2, 3 v ix (ac) input differential pair cross point voltage, ck and ck inputs (0.5* v ddq ) - 0.2 (0.5* v ddq ) + 0.2 v 1, 2, 4 1. input slew rate = 1v/ ns. 2. inputs are not recognized as valid until v ref stabilizes. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same.
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 14 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. operating, standby, and refresh currents t a = 0 c ~ 70 c; v ddq = v dd = 2.5v 0.2v symbol parameter/condition notes idd0 operating current: one bank; active/precharge; t rc = t rc (min) ; t ck = t ck (min) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1,2 idd1 operating current: one bank; active/read/precharge; burst = 2; t rc = t rc (min) ; cl=2.5; t ck = t ck (min) ; i out = 0ma; address and control inputs changing once per clock cycle 1,2 idd2p precharge power-down standby current: all banks idle; power-down mode; cke v il (max) ; t ck = t ck (min) 1,2 idd2n idle standby current: cs v ih (min) ; all banks idle; cke v ih (min) ; t ck = t ck (min) ; address and control inputs changing once per clock cycle 1,2 idd3p active power-down standby current: one bank active; power-down mode; cke v il (max) ; t ck = t ck (min) 1,2 idd3n active standby current: one bank; active/precharge; cs v ih (min) ; cke v ih (min) ; t rc = t ras (max) ; t ck = t ck (min) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1,2 idd4r operating current: one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2.5; t ck = t ck (min) ; i out = 0ma 1,2 idd4w operating current: one bank; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl=2.5; t ck = t ck (min) 1,2 idd5 auto-refresh current: t rc = t rfc (min) 1,2,3 idd6 self-refresh current: cke 0.2v 1,2 idd7 operating current: four bank; four bank interleaving with bl = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t rc = t rc (min) ; i out = 0ma. 1,2 1. idd specifications are tested after the device is properly initialized. 2. input slew rate = 1v/ ns. 3. current at 7.8 s is time averaged value of idd5 at t rfc (min) and idd2p over 7.8 s. all idd current values are calculated from device level. nt1gd64s8hb0fm nt1gd64s8hb0fn nt512d64sh8b0gm nt512d64sh8b0gn nt256d64sh4b0gm nt256d64sh4b0gn symbol pc2700 (6k) pc2100 (75b) pc2700 (6k) pc2100 (75b) pc2700 (6k) pc2100 (75b) idd0 1575 tbd 810 tbd 382 tbd ma idd1 1634 tbd 839 tbd 397 tbd ma idd2p 57 tbd 30 tbd 13 tbd ma idd2n 420 tbd 222 tbd 99 tbd ma idd3p 195 tbd 103 tbd 46 tbd ma idd3n 767 tbd 406 tbd 180 tbd ma idd4r 1705 tbd 875 tbd 415 tbd ma idd4w 1910 tbd 977 tbd 466 tbd ma idd5 3125 tbd 1585 tbd 770 tbd ma idd6 38 tbd 20 tbd 9 tbd ma idd7 4961 tbd 2503 tbd 1229 tbd ma
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 15 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions non-ecc, 16 bga devices, nt1gd64s8hb0fm / nt1gd64s8hb0fn note: devices are not to scale and are there as references only. 67.60 4.00+/-0.10 1.00+/- 0.1 front side 1.00+/- 0.10 detail a 2.55 0.60 detail b 0.45 0.25 max 199 13941 detail a detail b 4.00 20.00 31.75 6.00 2.15 11.40 4.20 1.80 47.40 3.80 max (2x) 1.80 2.45 back 63.60 note: all dimensions are typical with tolerances of +/- 0.15 unless otherwise stated . units: millimeters (inches)
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 16 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions non-ecc, 8 tsop devices, nt512d64sh8b0gm / nt512d64sh8b0gn 67.60 63.60 4.00+/-0.10 1.00+/- 0.1 front side 1.00+/- 0.10 detail a 2.55 0.60 detail b 0.45 0.25 max 199 13941 detail a detail b 4.00 20.00 31.75 6.00 2.15 11.40 4.20 1.80 47.40 3.80 max (2x) 1.80 2.45 24042 200 back note: all dimensions are typical with tolerances of +/- 0.15 unless otherwise stated . units: millimeters (inches)
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 17 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions non-ecc, 4 tsop devices, nt256d64sh40gm / nt256d64sh40gn 67.60 63.60 4.00+/-0.10 1.00+/- 0.1 front side 1.00+/- 0.10 detail a 2.55 0.60 detail b 0.45 0.25 max 199 13941 detail a detail b 4.00 20.00 31.75 6.00 2.15 11.40 4.20 1.80 47.40 3.00 max (2x) 1.80 2.45 24042 200 back note: all dimensions are typical with tolerances of +/- 0.15 unless otherwise stated . units: millimeters (inches)
nt1gd64s8hb0fm / nt512d64sh 8b0gm / nt256d64sh4b0gm nt1gd64s8hb0fn / nt512d64s h8b0gn / nt256d64sh4b0gn 1gb, 512mb and 256mb rev 1.0 18 nov 9, 2004 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. revision log rev date modification 0.1 may 11, 2004 initial release: 1gb: nt1gd64s8hb0gm C 75b/6k 512mb: nt512d64sh8b0fm C 75b/6k 256mb: nt256d64sh4b0fm C 75b/6k 0.2 sep 2, 2004 corrected part numbers as: nt1gd64s8hb0fm nt512d64sh8b0gm nt256d64sh4b0gm 1.0 nov 9, 2004 updated idd 333 and spd values for all modules added green part numbers nanya technology corporation hwa ya technology park 669 fu hsing 3rd rd., kueishan, taoyuan, 333, taiwan, r.o.c. tel: +886-3-328-1688 please visit our home page for more information: www.nanya.com nanya reserves the right to make changes or deletions without any notice to any of its products. nanya makes no guarantee, warr anty or representation regarding the suitability of its products for any particular purpose. nanya assumes no liability arising out of the application or use of its products. al l parameters can and do vary in its application and must be validated for each customer application by the customer?s technician. by purchasing nanya products, nanya does not convey a ny license under its patent rights not the rights of others. nanya products are not designed or intended or authorized for use in systems intended for the military or surgical implants or any other applications where life is involved or where injury or death may occur or the loss/corruption of data or the loss of system reliability or mission critical applica tions. should the buyer purchase or use nanya products in such unintended or unauthorized application, the buyer and user shall indemnify and hold nanya and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, all fees and expenses directly or indirectly arising from any claim of loss, injury or deat h associated with unintended or unauthorized use even if such claims alleges nanya was negligent regarding design or manufacture of the part. nanya and the nanya logo are trademark s of the nanya technology corporation. printed in taiwan ?2004

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